Operation:
Destination / Source -->; Destination
Compatibility: 68000 Family (see below)
Assembler Syntax:
DIVU.W <ea>, Dn 32/16 -->; 16r:16q
*DIVU.L <ea>, Dq 32/32 -->; 32q
*DIVU.L <ea>, Dr:Dq 64/32 -->; 32r:32q
* Applies to MC68020/MC68030/MC68040 only.
Attributes: Size = (Word, Long)
Description: Divides the unsigned destination operand by
the unsigned source operand and stores the unsigned
result in the destination. The instruction uses one of
three forms. The word form of the instruction divides
a long word by a word. The result is a quotient in the
lower word (least significant 16 bits) and the remainder
is in the upper word (most significant 16 bits) of the
result.
The first long form divides a long word by a long word.
The result is a long quotient; the remainder is discarded.
The second long form divides a quad word (in any two data
registers) by a long word. The result is a long-word
quotient and a long-word remainder.
Two special condition may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected and set before the inst-
ruction completes. If the instruction detects
an overflow, it sets the overflow condition
code and the operands are unaffected.
Condition Codes:
\c32220
X Not affected.
N Set if the quotient is negative. Cleared otherwise.
Undefined if overflow or divide by zero occurs.
Z Set if the quotient is zero. Cleared otherwise.
Undefined if overflow or divide by zero occurs.
V Set if the division overflow occurs; undefined if
divide by zero occurs. Cleared otherwise.
C Always cleared.
Instruction Format (word format):
\i1+---3Reg,-++u6Effective Address,3Mode,3Reg,
Instruction Fields (word format):
Register field -- Specifies any of the eight data registers.
This field always specifies the destination register.
Effective Address field -- Specifies the source operand.
Only data addresssing modes are allowed as shown:
\mBFF
Instruction Format (long format):
\i2-+--++---+u6Effective Address,3Mode,3Reg,-3Reg Dq,-1Sz,-------3Reg Dr,
Instruction Fields (long format):
Effective Address field -- Specifies the source operand.
Only data addresssing modes are allowed as shown:
\mBFF
Register Dq field -- Specifies a data register for the dest-
ination operand. The low-order 32 bits of the
dividend comes from this register, and the 32-
bit quotient is loaded into this register.
Sz field -- Selects a 32- or 64-bit division operation.
0 -- 32-bit dividend is in Register Dq.
1 -- 16-bit dividend is in Dr:Dq.
Register Dr field -- After the division, this register contains
the 32-bit remainder. If Dr and Dq are the same
register, only the quotient is returned.
Note: Overflow occurs if the quotient is larger than a 32-bit
unsigned integer.