Operation:
Destination / Source -->; Destination
Compatibility: MC68020/MC68030/MC68040
Assembler Syntax:
DIVSL.L <ea>, Dr:Dq 32/32 -->; 32r:32q
Attributes: Size = (Long)
Description: Divides the signed destination operand by the
signed source operand and stores the signed result in the
destination.
This instruction divides a long word by a long word. The
result is a long-word quotient and a long-word remainder.
Two special condition may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected and set before the inst-
ruction completes. If the instruction detects
an overflow, it sets the overflow condition
code and the operands are unaffected.
Condition Codes:
\c32220
X Not affected.
N Set if the quotient is negative. Cleared otherwise.
Undefined if overflow or divide by zero occurs.
Z Set if the quotient is zero. Cleared otherwise.
Undefined if overflow or divide by zero occurs.
V Set if the division overflow occurs; undefined if
divide by zero occurs. Cleared otherwise.
C Always cleared.
Instruction Format:
\i2-+--++---+u6Effective Address,3Mode,3Reg,-3Reg Dq,+--------3Reg Dr,
Instruction Fields:
Effective Address field -- Specifies the source operand.
Only data addresssing modes are allowed as shown:
\mBFF
Register Dq field -- Specifies a data register for the dest-
ination operand. The low-order 32 bits of the
dividend comes from this register, and the 32-
bit quotient is loaded into this register.
Register Dr field -- After the division, this register contains
the 32-bit remainder. If Dr and Dq are the same
register, only the quotient is returned.
Note: Overflow occurs if the quotient is larger than a 32-bit
signed integer. The assembler accepts TDIVS as an
alternative syntax for the DIVSL instruction.