Operation:
Registers -->; Destination
Source -->; Registers
Compatibility: 68000 Family
Assembler Syntax: (see ÒRegister ListsÓ below)
MOVEM register list, <ea>
MOVEM <ea>, register list
Attributes: Size = (Word, Long)
Description: Moves the contents of selected register to or
from consecutive memory locations starting at the
location specified by the effective address. A register is
selected if the bit in the mask field corresponding to that
register is set. The instruction size determines whether
16 or 32 bits of each register are transferred. In the
case of a word transfer to either address or data registers,
each word is sign extended to 32 bits, and the resulting
long word is loaded into the associated register.
Selecting the address mode also selects the mode of
operation of the MOVEM instruction, and only the control
modes, the predecrement mode, and the postincrement
mode are valid. If the effective address is specified by
one of the control modes, the registers are transferred
starting at the specified address, and the address is inc-
remented by the operand length (2 or 4) following each
transfer. The order of the registers is from data register
0 to data register 7, then from address register 0 to
address register 7.
If the effective address is specified by the predecrement
mode, only a register-to-memory operation is allowed.
The registers are stored starting at the specified address
minus the operand length (2 or 4), and the address is dec-
remented by the operand length following each transfer.
The order of storing is from address register 7 to address
register 0, then from data register 7 to data register 0.
When the instruction has completed, the decremented address
register contains the address of the last operand stored. For
the MC68020, MC68030, and MC68040, if the addressing
register is also moved to memory, the value written is the
initial register value decremented by the size of the oper-
ation. The MC68000 writes the initial register value
(not decremented).
If the effective address is specified by the postincrement mode,
only a memory-to-register operation is allowed. The registers
are loaded starting at the specified address; the address is inc-
remented by the operand length (2 or 4) following each
transfer. The order of loading is the same as that of control
mode addressing. When the instruction has completed, the
incremented address register contains the address of the last
operand plus the operand length. If the addressing register is
also loaded from memory, the memory value is ignored and the
register is written with the postincremented effective address.
Condition Codes:
Not affected.
Instruction Format:
\i2-+--+1dr,--+1Sz,u6Effective Address,3Mode,3Reg,0Register List Mask,
Instruction Fields (Postincrement source and destination):
dr field -- Specifies the direction of the transfer:
0 -- Register to memory.
1 -- Memory to register.
Sz field -- Specifies the size of the registers being transferred:
0 -- Word transfer.
1 -- Long transfer.
Effective Address field -- Specifies the memory address for the
operation. For register-to-memory transfers, only
control alterable addressing modes or the predecrement
addressing mode are allowed as shown:
\m2F8
For memory-to-register transfers, only control address-
ing modes or the postincrement addressing mode are
allowed as shown:
\m37B
Register List Mask field -- Specifies the register to be
transferred. The low-order bit corresponds to the
first register to be transferred; the high-order bit
corresponds to the last register to be transferred.
Thus, both for control modes and for the postincrement
mode addresses, the mask correspondence is:
\i11A7,1A6,1A5,1A4,1A3,1A2,1A1,1A0,1D7,1D6,1D5,1D4,1D3,1D2,1D1,1D0,
For the predecrement mode addresses, the mask
correspondence is reversed:
\i11D0,1D1,1D2,1D3,1D4,1D5,1D6,1D7,1A0,1A1,1A2,1A3,1A4,1A5,1A6,1A7,
Register Lists:
The assemblerÕs syntax for register lists is as follows:
1. A range of registers is specified with a hyphen (minus
sign) as in ÒA0-A3Ó. Note that ranges must
begin with the smaller of the two registers. All
data registers are considered smaller than all
address registers, so ÒD7-A0Ó is a legal range.
2. A set of distinct registers is specified by a list separated
by slashes (division signs) as in ÒA0/D7/D3Ó.
These may be in any order.
3. A combination of 1 and 2, such as ÒA0-A3/D3/D6-D7Ó
may be specified. The assembler just ignores registers
which are specified more than once, as in ÒA3/A2-A4Ó