Operation:
Destination Shifted by <count> -->; Destination
Compatibility: 68000 Family
Assembler Syntax:
LSR Dx, Dy
LSR #<data>, Dy
LSR <ea>
Attributes: Size = (Byte, Word, Long)
Description: Shifts the bits of the operand to the right. The carry bit
receives the last bit shifted out of the operand. The shift count for
the shifting of a register may be specified in two different ways:
1. Immediate -- The shift count is specified in the instr-
uction (shift range 1-8).
2. Register -- The shift count is the value in the data reg-
ister specified in instruction modulo 64.
The size of the operation can be specified as byte, word, or long.
An operand in memory can be shifted one bit only, and the operand
size is restricted to word.
Bits shifted out of the low-order bit go to both the carry and the
extend bits; the sign bit (MSB) is shifted into the high-order bit.
Condition Codes:
\c22202
X Set according to the last bit shifted out of the operand.
Unaffected for a shift count of zero.
N Set if the result is negative. Cleared otherwise.
Z Set if the result is zero. Cleared otherwise.
V Always cleared.
C Set according to the last bit shifted out of the operand.
Cleared for a shift count of zero.
Instruction Format (Register Shifts):
\i1+++-3Count/Reg,-2Size,1ir,-+3Reg,
Instruction Fields (Register Shifts):
Count/Register field -- Specifies shift count or register that contains the
shift count:
If ir = 0, this field contains the shift count. The values 1-7
represent counts of 1-7; value of zero represents 8.
If ir = 1, this field specifies the data register that
contains the shift count (modulo 64).
Size field -- Specifies the size of the operation:
00 -- Byte operation.
01 -- Word operation.
10 -- Long operation.
ir field:
If ir = 0, specifies immediate shift count.
If ir = 1, specifies register shift count.
Register field -- Specifies a data register to be shifted.
\bInstruction Format (Memory Shifts):
\i1+++---+-++u6Effective Address,3Mode,3Reg,
Instruction Fields (Memory Shifts):
Effective Address field -- Specifies the operand to be shifted. Only
memory alterable addressing modes are allowed as shown:
\m3F8