Operation:
SP-4 -->; SP; PC -->; (SP); PC + d -->; PC
Compatibility: 68000 Family
Assembler Syntax:
BSR <label>
Attributes: Size = (Byte, Word, Long*)
*(MC68020, MC68030, MC68040 only)
Description: Pushes the long word address of the instruction
immediately following the BSR instruction onto the system
stack. The PC contains the address of the instruction plus two.
Program execution continues at location (PC) + displace-
ment. The PC contains the address of the instruction
word of the BRA instruction plus two. The displacement is a
twos compliment integer that represents the relative distance
in bytes from the current PC to the 16-bit displacement
(the word immediately following the instruction) is used.
If the 8-bit displacement field in the instruction word is all
ones ($FF), the 32-bit displacement (long word immediately
following the instruction) is used. Condition code cc specifies
one of the following conditions.
Condition Codes:
Not affected.
Instruction Format:
\i3-++----+88-bit Displacement,016-bit Displacement if 8-bit Displacement = $00,032-bit Displacement if 8-bit Displacement = $FF,
Instruction Fields:
Condition field -- The binary code for one of the
conditions listed in the table.
8-bit Displacement field -- Twos complement integer
specifying the number of bytes between the branch
instruction and the next instruction to be executed
if the condition is met.
16-bit Displacement field -- Used for the displacement when
the 8-bit displacement field contains $00.
32-bit Displacement field -- Used for the displacement when
the 8-bit displacement field contains $FF.
Note: A branch to the immediately following instruction auto-
matically uses the 16-bit displacement format because
the 8-bit displacement field contains $00 (zero offset).