Operation:
Source + Destination -->; Destination
Compatibility: 68000 Family
Assembler Syntax:
ADDX Dy, Dx
ADDX -(Ay), -(Ax)
Attributes: Size = (Byte, Word, Long)
Description: Adds the source operand to the destination operand
along with the extend bit and stores the result in the
destination location. The operands cas be addressed in two
ways:
1. Data register to data register.
2. Memory to memory (Pre-decrement mode)
The size of the operation can be specified as byte, word, or
long.
Condition Codes:
\c22222
X Set the same as the carry bit.
N Set if the result is negative. Cleared otherwise.
Z Cleared if the result is nonzero. Unchanged otherwise.
V Set if an overflow is generated. Cleared otherwise.
C Set if a carry is generated. Cleared otherwise.
Note: Normally the Z condition code bit is set via programming before
the start of an operation. This allows successful tests for zero results
upon completion of multiple-precision operations.
Instruction Format:
\i1++-+3Reg Rx,+2Size,--1RM,3Reg Ry,
Instruction Fields:
Register Rx field -- Specifies the destination register:
If RM = 0, specifies a data register.
If RM = 1, specifies an address register for
predecrement mode.
Size field -- Specifies the size of the operation:
00 -- Byte operation.
01 -- Word operation.
10 -- Long operation.
RM field -- Specifies the operand addressing mode:
0 -- the operation is data register to data register.
1 -- the operation is memory to memory.
Register Ry field -- Specifies the source register:
If RM = 0, specifies a data register.
If RM = 1, specifies an address register for
predecrement mode.
Related Instructions:
ADD,401
ADDA,402
ADDI,403
ADDQ,404
.404406