Operation: Source * Destination -->; Destination
Compatability: 68000 Family
Assembler Syntax:
MULU.W <ea>, Dn 16 x 16 -->; 32
MULU.L* <ea>, Dl 32 x 32 -->; 32
MULU.L* <ea>, Dh:Dl 32 x 32 -->; 64
* Applies to MC68020/MC68030/MC68040 only.
Attributes: Size = (Word, Long)
Description: Multiplies two unsigned operands yielding an
unsigned result. This instruction has a word operand form
and a long-word operand form.
In the word form, the multiplier and multiplicand are
both word operands, and the result is a long-word operand.
A register operand is the low-order word; the upper word
of the register is ignored. All 32 bits of the product are
saved in the destination data register.
In the long form, the multiplier and multiplicand are both
long-word operands, and the result is either a long word or
a quad word. The long-word result is the low-order 32
bits of the quad word result; the high-order 32 bits of the
product are discarded.
Condition Codes:
\c32220
X Not affected.
N Set if the result is negative. Cleared otherwise.
Z Set if the result is zero. Cleared otherwise.
V Set if overflow. Cleared otherwise.
C Always cleared.
Note: Overflow (V = 1) can occur only when multiplying 32-bit
operands to yield a 32-bit result. Overflow occurs if the
high-order 32 bits of the quad-word product are not the
sign extension of the low-order 32 bits.
Instruction Format (word form):
\i1++--3Reg,-++u6Source,3Mode,3Reg,
Instruction Fields (word form):
Register field -- Specifies a data register as the destination.
Effective Address field -- Specifies the source operand. Only
data addressing modes are allowed as shown:
\mBFF
Instruction Format (long form):
\i2-+--++----u6Source,3Mode,3Reg,-3Reg Dl,-1Sz,-------3Reg Dh,
Instruction Fields (long form):
Effective Address field -- Specifies the source operand. Only
data addressing modes are allowed as shown:
\mBFF
Register Dl field -- Specifies a data register for the dest-
ination operand. The 32-bit multiplicand comes
from this register, and the low-order 32 bits of
the product are loaded into the register.
Sz field -- Selects a 32- or 64-bit product.
0 -- 32-bit product to be returned to Register Dl.
1 -- 64-bit product to be returned to Dh:Dl.
Register Dh field -- If Size is one, specifies the data register
into which the high-order 32 bits of the product are
loaded. If Dh = Dl and Size is one, the results of the
operation are undefined. Otherwise, this field is
unused.
Related Instructions:
MULS,464
.464466