**Operation:**

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Destination / Source -->; Destination

**Compatibility:** 68000 Family (see below)

**Assembler Syntax:**

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DIVU.W <ea>, Dn` `

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32/16 -->; 16r:16q

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*DIVU.L <ea>, Dq` `

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32/32 -->; 32q

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*DIVU.L <ea>, Dr:Dq` `

64/32 -->; 32r:32q

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* Applies to MC68020/MC68030/MC68040 only.

**Attributes:** Size = (Word, Long)

**Description:** Divides the unsigned destination operand by

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the unsigned source operand and stores the unsigned

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result in the destination. The instruction uses one of

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three forms. The word form of the instruction divides

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a long word by a word. The result is a quotient in the

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lower word (least significant 16 bits) and the remainder

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is in the upper word (most significant 16 bits) of the

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result.

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The first long form divides a long word by a long word.

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The result is a long quotient; the remainder is discarded.

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The second long form divides a quad word (in any two data

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registers) by a long word. The result is a long-word

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quotient and a long-word remainder.

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Two special condition may arise during the operation:

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1. Division by zero causes a trap.

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2. Overflow may be detected and set before the inst-

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ruction completes. If the instruction detects

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an overflow, it sets the overflow condition

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code and the operands are unaffected.

**Condition Codes:**

\c32220

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X Not affected.

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N Set if the quotient is negative. Cleared otherwise.

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Undefined if overflow or divide by zero occurs.

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Z Set if the quotient is zero. Cleared otherwise.

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Undefined if overflow or divide by zero occurs.

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V Set if the division overflow occurs; undefined if

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divide by zero occurs. Cleared otherwise.

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C Always cleared.

**Instruction Format (word format):**

\i1+---3Reg,-++u6Effective Address,3Mode,3Reg,

**Instruction Fields (word format):**

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Register field -- Specifies any of the eight data registers.

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This field always specifies the destination register.

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Effective Address field -- Specifies the source operand.

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Only data addresssing modes are allowed as shown:

\mBFF

**Instruction Format (long format):**

\i2-+--++---+u6Effective Address,3Mode,3Reg,-3Reg Dq,-1Sz,-------3Reg Dr,

**Instruction Fields (long format):**

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Effective Address field -- Specifies the source operand.

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Only data addresssing modes are allowed as shown:

\mBFF

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Register Dq field -- Specifies a data register for the dest-

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ination operand. The low-order 32 bits of the

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dividend comes from this register, and the 32-

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bit quotient is loaded into this register.

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Sz field -- Selects a 32- or 64-bit division operation.

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0 -- 32-bit dividend is in Register Dq.

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1 -- 16-bit dividend is in Dr:Dq.

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Register Dr field -- After the division, this register contains

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the 32-bit remainder. If Dr and Dq are the same

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register, only the quotient is returned.

Note: Overflow occurs if the quotient is larger than a 32-bit

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unsigned integer.